Currently, semiconductor dynamic random access memory (DRAM) memory devices are available for silicon on insulator SOI and for complementary metal-oxide semiconductor (CMOS) integrated circuits (IC)s. An SOI type thin film transistor is used as a component in three-dimensional integrated circuits and liquid crystal displays. The SOI type thin film transistor includes a power source/drain region or active region formed at a semiconductor layer on a semiconductor substrate with an insulation film thereunder. In SOI integrated circuits, the active region is isolated from the semiconductor substrate. The SOI type thin film transistor includes a junction capacitance of the active region that is extremely small allowing operation at high speeds with low power consumption. SOI type thin film transistors, such as, metal oxide semiconductor field-effect transistors (thin film SOIMOSFET) may include a 1 G bit (gigabit) DRAM (dynamic random access memory).
U.S. Pat. No. 5,822,264 ('264 patent) to Tomishima et al. discloses a dynamic semiconductor memory device with SOI structure and body refresh circuitry. Essentially, the body refresh operation discharges majority carriers which are stored in a floating body region. A floating body effect is an effect of dependence of the body potential of a transistor. The transistor's body forms a capacitor against the insulated substrate. The charge accumulates on the capacitor and may cause adverse effects, such as, opening of parasitic transistors in the structure and causing off-state leakages, resulting in higher current consumption and in case of a DRAM cell, loss of information from the memory cells. Thus, parasitic floating-body effects are generally associated with partially depleted transistors.
The '264 patent discloses a body refresh function in addition to data refresh operation. The '264 patent discloses a write circuitry including column select circuitry to provide a body refresh potential or GND (ground) to each bit line during the body refresh period.
Typically, high performance DRAM cells with SOI access transistors have a high leakage rate and thereby lose data through sub-threshold leakage. As a result, a ground (GND) pre-charge scheme that keeps the BL/BLB (bit line, and bit line bar) at GND during a retention period will destroy high data (logic 1) on the DRAM cell node. Alternatively, a voltage (VDD) pre-charge scheme that holds BL/BLB at a specified VDD during a retention period can hold data longer. VDD pre-charge can reduce the cell leakage through a surface channel of a cell access transistor while GND pre-charge may loose data during a retention period.
In another example of the VDD pre-charge scheme, the bit line (BL) or bit line bar (BLB) connected to high data containing cells are kept at a pre-charge state (high voltage) until the BL and BLB are pulled down (reduced to zero). When both the bit line and cell node have a high voltage, the potential of the floating body is high. This results in high leakage current when the bit line or bit line bar (reference bit line) is pulled down (reduced to zero). The occurrence of high current leakage may result in data destruction.
Another example of a GND sensing scheme is when the BL or BLB is connected to high data containing cells which keeps the pre-charge state, i.e. GND level, without toggling. This scenario results in continuous leakage and results in lower data retention time.
However, in a VDD (voltage) pre-charge scheme in which the BL or BLB keeps the VDD level while maintaining high data on a cell node, the floating body is charged to a high voltage due to junction leakage current from the source and drain of the cell access transistor. Assuming a long enough time to charge the floating body, floating body potential can be close to VDD. This leads to destruction of the stored data because the increased floating body increases channel leakage. Therefore, keeping body potential at a low level is desirable for a VDD pre-charge scheme.
In a OND pre-charge scheme, the pre-charge state of BL is GND and is intended to automatically refresh the body. However, both OND and VDD pre-charge schemes increase the body potential and lead to short retention of data. The VDD pre-charge scheme prevents high data loss while the BL is in pre-charge state, but requires refreshing the floating body to achieve data retention. Thus, data in a typical DRAM cell is susceptible to leakage resulting in loss of data. It would therefore be desirable to solve the problem of retention of data in a SOI-DRAM cell on an integrated circuit.